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Cortex-M4 instructions The processor implements the ARMv7-M Thumb instruction set. Table 3.1 shows the Cortex-M4 instructions and their cycle counts. The Cortex-M4 Memory Map. – Bit-band Operations. – Cortex-M4 Program Image and Endianness. • ARM Cortex-M4 Processor Instruction Set. Cortex-M4 Processor Features. • 32-bit Reduced Instruction Set Computing (RISC) processor. • Harvard architecture. – Separated data bus and instruction bus. The following information was excerpted from the ARM Cortex-M4 Processor Technical · Reference Manual (r0p1). Basic instruction cycle counts are found in When the instruction is executed, the value of Rn[0] determines whether the instruction stream will be decoded as ARM or THUMB instructions. Figure 4-2: BranchThe table summarizes the Cortex-M4 processor instruction set. For brevity, not all load and store addressing modes are shown in the table.